1. Field of the Invention
This invention relates to a technique for controlling a clock signal, especially to a method and circuit for stopping a clock signal. This invention is applicable to a control method and circuit for providing a clock to a central processing unit.
2. Description of the Related Art
Enormous improvement has been achieved for central processing units generally called CPU or MPU. The operational frequency of the fastest devices has reached the order of gigahertz. Although the frequency will be higher in future, there is a program that the power consumption of such devices will become greater in relation to the operational frequency as the central processing units are generally formed by MOS devices. Improvement of performance causes increase of power consumption, which reduces battery operation time of products to which the central processing units are applied. To solve this problem, elaborately controlling the clock for the central processing units has been proposed. Low power design is often introduced by reducing the frequency of the clock based on the types of processes executed.
Japanese Laid-Open publication H8-314716 discloses a clock control method in which a clock stop controller, in collaboration with a bus controller, stops the provision of a central processing unit clock signal to the central processing unit core by continuously asserting a bus request signal responding to a write request to a certain address. To resume from the clock stop mode, the controller issues a bus acknowledge response signal responding to a predetermined asynchronous input signal thereby canceling the prohibition state of the central processing unit clock signal.
In the above-mentioned technique, however, it becomes necessary to redesign the bus controller which is originally not related to the control of the clock for the central processing unit. It is naturally desirable to modify or add a circuit directly related to the clock control while leaving other circuits around the central processing unit intact in terms of design efficiency and developing term. It is also desirable not to redesign the central processing unit itself only for the clock control purpose.